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| DS1204V DS1204V Electronic Key FEATURES PIN ASSIGNMENT * Cannot be deciphered by reverse engineering * Partitioned memory thwarts pirating * User-insertable packaging sion allows personal posses- DALLAS DS1204V ELECTRONIC KEY * Exclusive blank keys on request * Appropriate identification can be made with a 64-bit reprogrammable memory SIDE * Unreadable 64-bit security match code virtually prevents deciphering by exhaustive search with over 1019 possibilities * 128 bits of secure read/write memory create additional barriers by permitting data changes as often as needed 1 5 BOTTOM: PIN VIEW 1.0 IN See Mech. Drawings Section * Rapid erasure of identification security match code and secure read/write memory can occur if tampering is detected * Low-power CMOS circuitry * Four million bps data rate * Durable and rugged * Applications include software authorization, gray market software protection, proprietary data, financial transactions, secure personnel areas, and system access control PIN DESCRIPTION Pin 1 - VCC Pin 2 - RST Pin 3 - DQ Pin 4 - CLK Pin 5 - GND +5 Volts Reset Data Input/Output Clock Ground DESCRIPTION The DS1204V Electronic Key is a miniature security system that stores 64 bits of user-definable identification code and a 64-bit security match code that protects 128 bits of read/write nonvolatile memory. The 64-bit identification code and the security match code are programmed into the key via a special program mode operation. After programming, the key follows a procedure with a serial format to retrieve or update data. Interface cost to a microprocessor is minimized by on-chip circuitry that permits data transfer with only three signals: Clock (CLK), Reset (RST), and Data Input/Output (DQ). Low pin count and a guided entry for mating receptacle overcome mechanical problems normally encountered with conventional integrated circuit packaging, making the device transportable and user-insertable. OPERATION - NORMAL MODE The Electronic Key has two modes of operation: normal and program. The block diagram (see Figure 1) illustrates the main elements of the key when used in the normal mode. To initiate data transfer with the key, RST is taken high and 24 bits are loaded into the command 021798 1/10 DS1204V register on each low-to-high transition of the CLK input. The command register must match the exact bit pattern that defines normal operation for read or write, or communications are ignored. If the command register is loaded properly, communications are allowed to continue. The next 64 cycles to the key are reads. Data is clocked out of the key on the high-to-low transition of the clock from the identification memory. Next, 64 write cycles must be written to the compare register. These 64 bits must match the exact pattern stored in the security match memory. If a match is not found, access to additional information is denied. Instead, random data is output for the next 128 cycles when reading data. If write cycles are being executed, the write cycles are ignored. If a match is found, access is permitted to a 128-bit read/ write nonvolatile memory. Figure 2 is a summary of normal mode operation and Figure 3 is a flow chart of the normal mode sequence. BLOCK DIAGRAM - NORMAL MODE Figure 1 D/Q CLK CONTROL LOGIC 64-BIT IDENTIFICATION RST 64-BIT SECURITY MATCH COMPARE REGISTER 128-BIT SECURE MEMORY COMMAND REGISTER RANDOM DATA SEQUENCE - NORMAL MODE Figure 2 PROTOCOL IDENTIFICATION SECURITY MATCH COMMAND WORD 64 READ CYCLES 64 WRITE CYCLES MATCH SECURE MEMORY 128 READ OR WRITES 021798 2/10 DS1204V FLOW CHART - NORMAL MODE Figure 3 RESET HIGH WRITE COMMAND PROTOCOL NO MATCH FOR READ OR WRITE READ 64 BITS IDENTIFICATION WRITE 64 BITS SECURITY MATCH NO MATCH OUTPUT GARBLED DATA READ OR WRITE 128 BITS BASED ON PROTOCOL SECURE NV RAM STOP RESET LOW OUTPUT IN HIGH Z PROGRAM MODE The block diagram in Figure 4 illustrates the main elements of the key when used in the program mode. To initiate the program mode, RST is driven high and 24 bits are loaded into the command register on each low-to-high transition of the CLK input. The command register must match the exact pattern that defines pro- gram operation. If an exact match is not found, the remainder of the program cycle is ignored. If the command register is properly loaded, then the 128 bits that follow are written to the identification memory and the security match memory. Figure 5 is a summary of program mode operation and Figure 6 is a flow chart of program mode operation. 021798 3/10 DS1204V BLOCK DIAGRAM - PROGRAM MODE Figure 4 D/Q CLK 64-BIT IDENTIFICATION CONTROL LOGIC RST 64-BIT SECURITY MATCH COMMAND REGISTER SEQUENCE - PROGRAM MODE Figure 5 PROTOCOL IDENTIFICATION SECURITY MATCH COMMAND WORD 64 WRITE CYCLES 64 WRITE CYCLES COMMAND WORD Each data transfer for the normal and program mode begins with a three-byte command word as shown in Figure 7. As defined, the first byte of the command word specifies whether the 128-bit nonvolatile memory will be written into or read. If any one of the bits of the first byte of the command word fails to meet the exact pattern of read or write, the data transfer will be aborted. The 8-bit pattern for read is 01100010. The pattern for write is 10011101. The first two bits of the second byte of the command word specify whether the data transfer to follow is a program or normal cycle. The bit pattern for program is 0 in bit 0 and 1 in bit 1. The program mode can be selected only when the first byte of the command word specifies a write. If the program mode is specified and the first byte of the command word does not specify a write, data transfer will be aborted. The bit pattern that selects the normal mode of operation is 1 in bit 0 and 0 in bit 1. The other two possible combinations for the first two bits of byte 2 will cause data transfer to abort. The remaining six bits of byte 2 and the first seven bits of byte 3 form unique patterns that allow multiple keys to reside on a common bus. As such, each respective code pattern must be written exactly for a given device or data transfer will abort. Dallas Semiconductor has five patterns available as standard products per the chart in Figure 7. Each pattern corresponds to a specific part number. Under special contract with Dallas Semiconductor, the user can specify any bit pattern other than those specified as unavailable. The bit pattern as defined by the user must be written exactly or data transfer will abort. The last bit of byte 3 of the command word must be written to logic 1 or data transfer will abort. NOTE: Contact the Dallas Semiconductor sales office for a special command word code assignment that makes possible an exclusive blank key. 021798 4/10 DS1204V FLOW CHART - PROGRAM MODE Figure 6 RESET HIGH WRITE COMMAND PROTOCOL NO MATCH PROGRAM MODE WRITE 64 BITS IDENTIFICATION WRITE 64 BITS SECURITY MATCH STOP RESET LOW OUTPUT IN HIGH Z RESET AND CLOCK CONTROL All data transfers are initiated by driving the RST input high. The RST input serves three functions. First, it turns on control logic, which allows access to the command register for the command sequence. Second, the RST signal provides a power source for the cycle to follow. To meet this requirement, a drive source for RST of 2 mA @ 3.5 volts is required. However, if the VCC pin is connected to a 5-volt source within nominal limits, the RST is not used as a source of power and input levels revert to normal VIH and VIL inputs with a drive current requirement of 500 A. Third, the RST signal provides a method of terminating data transfer. A clock cycle is a sequence of a falling edge followed by a rising edge. For data inputs, the data must be valid during the rising edge of a clock cycle. Command bits and data bits are input on the rising edge of the clock and data bits are output on the falling edge of the clock. The rising edge of the clock returns the DQ pin to a high impedance state. All data transfer terminates if the RST pin is low and the DQ pin goes to a high impedance state. When data transfer to the key is terminated using RST, the transition of RST must occur while the clock is at a high level to avoid disturbing the last bit of data. Data transfer is illustrated in Figure 8 for normal mode and Figure 9 for program mode. 021798 5/10 DS1204V COMMAND WORD Figure 7 0 R W R W R W R W R W R W R W R W BYTE 1 X X X X X X P P BYTE 2 23 1 X X X X X X X BYTE 3 0 DS1204V-G01 1 0 0 0 1 0 0 0 0 0 0 P 0 P 0 BYTE 2 BYTE 3 0 DS1204V-G02 1 0 0 0 1 0 0 0 0 1 0 P 0 P 0 BYTE 2 BYTE 3 0 DS1204V-G03 1 0 0 0 1 0 0 1 0 0 0 P 0 P 0 BYTE 2 BYTE 3 0 DS1204V-G04 1 0 0 0 1 0 0 1 0 1 0 P 0 P 0 BYTE 2 BYTE 3 0 DS1204V-G05 1 0 0 0 1 1 0 0 0 0 0 P 0 P 0 BYTE 2 BYTE 3 KEY CONNECTIONS The key is designed to be plugged into a standard 5-pin, 0.1-inch center SIP receptacle (SAMTEC SS-105 or equivalent). A guide is provided to prevent the key from being plugged in backwards and aid in alignment of the receptacle. For portable applications, contact to the key pins can be determined to ensure connection integrity before data transfer begins. CLK, RST, and DQ all have internal 20K ohm pulldown resistors to ground that can be sensed by a reading device. 021798 6/10 DS1204V DATA TRANSFER - NORMAL MODE Figure 8 CLOCK RESET 0 R/W 1 R/W 23 1 D0 D63 Q0 Q63 DQ0 DQ126 DQ127 COMMAND WORD READ 64 BITS WRITE 64 BITS READ/WRITE 128 BITS DATA TRANSFER - PROGRAM MODE Figure 9 CLOCK CLK RESET 0 R/W 1 R/W 2 23 1 Q0 Q1 Q62 Q63 Q0 Q1 Q62 Q63 COMMAND WORD WRITE 64 BITS WRITE 64 BITS 021798 7/10 DS1204V ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature -0.5V to +7.0V 0C to 70C -40C to +70C * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER Logic 1 Logic 0 RESET Logic 1 Supply SYMBOL VIH VIL VIHE VCC MIN 2.0 -0.3 3.5 4.5 5.0 5.5 +0.8 TYP MAX UNITS V V V V (0C to 70C) NOTES 1, 8, 10 1 1, 9, 11 1 DC ELECTRICAL CHARACTERISTICS PARAMETER Input Leakage Output Leakage Output Current @2.4V Output Current @0.4V RST Input Resistance D/Q Input Resistance CLK Input Resistance RST Current @3.0V Active Current Standby Current SYMBOL IIL ILO IOH IOL ZRST ZDQ ZCLK IRST ICC1 ICC2 10 10 10 -1 MIN TYP (0C to 70C; VCC = 5V + 10%) MAX +500 +500 UNITS A A mA +2 60 60 60 2 6 2.5 mA K ohms K ohms K ohms mA mA mA 6, 9, 13 6 6 NOTES 4 CAPACITANCE PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN TYP MAX 5 7 UNITS pF pF (tA = 25C) NOTES 021798 8/10 DS1204V AC ELECTRICAL CHARACTERISTICS PARAMETER Data to CLK Setup CLK to Data Hold CLK to Data Delay CLK Low Time CLK High Time CLK Frequency CLK Rise & Fall RST to CLK Setup CLK to RST Hold RST Inactive Time RST to I/O High Z SYMBOL tDC tCDH tCDD tCL tCH fCLK tR, tF tCC tCCH tCWH tCDZ 125 125 DC 500 1 40 125 MIN 35 40 TYP (0C to 70C, VCC = 5V + 10%) MAX UNITS ns ns 100 ns ns ns 4.0 MHz ns s ns ns 50 ns NOTES 2, 7 2, 7 2, 3, 5, 7 2, 7 2, 7 2, 7 2, 7 2, 7 2, 7 2, 7, 14 2, 7 TIMING DIAGRAM: WRITE DATA tCWH RESET tCC tCL tR tF CLOCK tDC tCdh DATA INPUT/OUTPUT R/W R/W tCH R/W tCCH TIMING DIAGRAM: READ DATA tCWH RESET tCC CLOCK tDC R/W tCDD tCDZ 021798 9/10 DS1204V NOTES: 1. All voltages are referenced to GND. 2. Measured at VIH = 2.0 or VIL = .8V and 10ns maximum rise and fall time. 3. Measured at VOH = 2.4 volts and VOL = 0.4 volts. 4. For CLK, D/Q, and RST. 5. Load capacitance = 50 pF. 6. Measured with outputs open. 7. Measured at VIH of RST > 3.5V when RST supplies power. 8. Logic 1 maximum is VCC + 0.3 volts if the VCC pin supplies power and RST + 0.3 volts if the RST pin supplies power. 9. Applies to RST when VCC < 3.5V. 10. Input levels apply to CLK, DQ, and RST while VCC is within nominal limits. When VCC is not connected to the key, then RST input reverts to VIHE. 11. RST logic 1 maximum is VCC + 0.3 volts if the VCC pin supplies power and 5.5 volts maximum if RST supplies power. 12. Each DS1204V is marked with a 4-digit code AABB. AA designates the year of manufacture. BB designates the week of manufacture. 13. Average AC RST current can be determined using the following formula: ITOTAL = 2 + ILOAD DC + (4 x 10-3) (CL + 140)f ITOTAL and ILOAD are in mA; CL is in pF; f is in MHz. Applying the above formula, a load capacitance of 50 pF running at a frequency of 4.0 MHz gives an ITOTAL of 5 mA. 14. When RST is supplying power tCWH must be increased to100 ms average. 021798 10/10 |
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